Multi channel pulse repetition frequency tracker b

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Abstract: in the radar seeker of anti radiation missile, the real-time performance of signal tracker is one of the important factors affecting the system performance. This paper introduces a multi-channel pulse repetition frequency tracker based on the rich resources of high-performance FPGA, which solves the real-time problem of signal tracking in dense signal environment and reduces the volume of the system. Through experimental verification, its indexes meet the design requirements

key words: anti radiation missile signal tracking field programmable gate array

with the rapid development of high technology, modern war is not only a battle in the traditional battlefield, but electronic warfare has become one of the important factors determining the victory or defeat of the war. Anti radiation missile plays an important role in electronic warfare. It can effectively suppress or destroy the radar in the enemy's weapon system, make the enemy's weapon system lose its attack ability, obtain air control and give full play to its own air superiority. In the anti radiation missile, the radar seeker guides the attack target. It intercepts the signal of the target radar and detects the incident angle of the signal, which is transmitted to the missile control system to guide the missile to track the target until it hits

The function of PRF> is to select the signal frequency of the radar seeker. In the increasingly complex electromagnetic environment, the spatial signal density has reached 500000 ~ 1 million pulses/s, which is at least equivalent to the sum of hundreds of radiation sources. Therefore, the signal intercepted by the signal receiver is usually the signal of more than one radar, often including many. The PRF tracker is to select the radar signal to be intercepted from the signal stream containing multiple radars and send it to the later signal processor. As shown in Fig. 1, the signal received by the receiver includes multiple signals. After selection by the pulse repetition rate tracker, only one signal is output to the subsequent signal processor. At present, there are three main methods to realize PRF Tracker: pure soft mode, semi soft and semi hard mode and pure hard mode. The pure soft mode uses high-speed DSP to complete all functions. This mode will affect the real-time performance of the system in the modern dense signal environment. In order to realize the tracking of multi-channel signals, multiple DSPs are required, which will cause the huge volume of the system. The semi soft and semi hard mode uses DSP and hardware circuit to complete some functions respectively, which has the same disadvantages as the former mode. In the pure hard mode, FPGA or CPLD is used to realize all the functions of tracking signal, which has the advantages of good real-time performance and stable performance. It can meet the requirements of the current complex electromagnetic environment, and has high integration, which can realize the miniaturization of the system

based on the characteristics of rich resources and easy programming of FPGA, this paper designs a pure hard pulse repetition rate tracker to realize signal tracking in dense signal environment, and integrates multi-channel parallel tracker into one FPGA, which simplifies the system structure and reduces the volume

1 PRF tracker principle

1.1 PRF tracker

in order to separate a signal from a dense signal flow, it is necessary to know the pulse repetition frequency and pulse repetition period (PRI) type of the signal. This part of work is usually completed by the signal preprocessor of radar reconnaissance system or anti radiation missile. Pulse repetition rate is an important parameter to identify radar, because it is the most characteristic signal parameter of radar. The most characteristic means that the performance of radar is greatly affected by the pulse repetition frequency used. For example, for conventional radar, the value of pulse repetition frequency determines the maximum unambiguous distance and maximum unambiguous radial velocity of radar. Pulse repetition period (PRI) is the reciprocal of pulse repetition frequency, which can be roughly divided into three types: fixed, jump and stagger. The interval between each pulse of the fixed PRI signal is constant; If the PRI of the signal is added with artificial random jump, the jump PRI signal is formed, and the change value of PRI can reach 15% of the average value of pulse repetition period; Stagger PRI signal consists of multiple pulses with different intervals to form a signal sequence frame. The sum of pulse repetition periods is called frame period, and the small interval between frame periods is called small period. Generally, the frame period is fixed

according to the above analysis, in order to realize the real-time tracking of various PRI types of signals, a pulse repetition rate tracker circuit is designed in FPGA, and its schematic diagram is shown in Fig. 2

as can be seen from Figure 2, the tracker includes repetition period registers 0 ~ 7, stagger register, output gate register, repetition period counter, output gate counter, output controller and other units. The stagger register stores the number of small cycles of stagger PRI signal, that is, the number of parameters; The repetition period registers 0 to 7 store each repetition period of the signal. At present, the stagger radar generally does not exceed 8 staggers, so there are 8 repetition period registers. The stagger stored in the stagger register controls each repetition period register. For example, if the stagger number is equal to 3, only 0 ~ 2 repetition cycle registers are valid, and the other 5 are useless. If the stagger number is equal to 1, only the repetition period register No. 0 is valid, which is equivalent to the case of fixed PRI signal. The output gate register stores the gate width, and its value is mainly determined by the change of jump PRI signal. If the variation is large, the output gate width should also be large, so as to select the signal to be intercepted. The numerical relationship can be expressed as: gate width = PRI variation + pulse width + constant a. Constant a is an adjustment parameter, which can be determined according to the debugging situation. The repetition period counter is the core device of the tracker. It determines when to start counting according to the arrival of the signal pulse. The counting period is the value in the repetition period register, and the stored value of each effective repetition period register is used circularly. Its output is sent to the output gate counter, which determines the width of the gate according to the value in the output gate register. The output controller is the main logic control unit, which controls the work of the whole tracker. The function of the output controller also includes judging whether the signal is intercepted successfully, whether the signal is lost, etc

1.2 signal filter

the rapid increase in the number of various electronic countermeasure equipment makes the radar seeker system in a highly dense signal environment, and the real-time performance of pulse repetition frequency tracker is tested. Based on the above considerations, a signal filter is designed at the front end of the tracker to dilute the signal pulse flow and reduce the pressure of the tracker. The schematic diagram of the signal filter is shown in Figure 3

The core of

signal filter is correlation comparator, and FPGA provides convenient conditions for the implementation of correlation comparator. In this system, two correlation comparators are used, one for signal carrier frequency filtering and the other for signal pulse width filtering. As can be seen from Figure 3, only the signal with carrier frequency and pulse width within a certain range can pass through the filter, that is, the signal is screened. In the modern complex electromagnetic environment, there are quite a lot of signals with similar carrier frequency and pulse width. At the same time, the upper and lower limits of the comparator can not be too close. In this way, the output of the filter is not limited to one signal, and even this greatly dilutes the signal flow. This diluted signal flows to the tracker, which helps to improve the real-time performance of the tracker and intercept the signal successfully

2 system implementation

the system block diagram is shown in Figure 4. The whole system is composed of DSP and FPGA. An 8-channel tracker is designed in FPGA, which can track up to 8 signals at the same time. DSP is responsible for controlling the work of each tracker, including loading parameters and enabling each tracker, and transmitting data with the main control computer on the missile through HPI (upper computer interface)

because all trackers are implemented in pure hardware, it takes little DSP processing time. DSP only needs to load the signal parameters transmitted by the main control computer into the tracker and send the start command. The rest of the work is completed automatically by the tracker without DSP intervention, so that DSP has a lot of time to perform other computing tasks

2.1 FPGA device selection

this design adopts apex series ep20k200eqi chip of Altera company. Apex series FPGA is a high-end product of Altera company. It is the first programmable logic device in the industry that integrates SOPC (system-on-a-programmable-chip) integrated circuit. It has high integration, can provide 2.5 million gates and 50000 logic units at most, and can provide 440000 bit ram without reducing logic units. Low power design, using dual voltage system, core voltage 1.8V, I/O voltage 3.3V, compatible with a variety of interface standards

ep20k200eqi chip is an industrial chip, which is packaged with 240 pin PQFP. The number of user I/O pins is 168 and 8320 logic units are provided, but the chip area is only 34.5mm34.5mm. In this design, the logic unit occupied by each tracker is 7%, and the total logic unit occupied by 8-way tracker plus some auxiliary circuits is 60%. There is still chip resources left, leaving room for the improvement of system functions in the future

2.2 FPGA chip configuration

apex series FPGA chips are devices based on SRAM technology. Due to the volatility of SRAM, the configuration information in the chip will be lost after power failure, so the configuration data must be reloaded every time the system is powered on. Altera provides a series of configuration devices to store configuration data and load FPGA when powered on. In this design, epc2 of Altera company is selected. The biggest advantage is that epc2 is a flash device, which can be programmed repeatedly, which eliminates the disadvantage that the previous Prom configuration device can only be written once, and greatly facilitates system debugging and product upgrading. When the designed product needs to be improved, just rewrite the content in epc2, which shortens the product R & D cycle

in the design, it should be noted that the capacity of epc2 is 1.6Mb, and the number of configuration chips required varies according to the capacity of FPGA chip. The ep20k200eqi chip used in this design has a capacity of 1.9mb, so two epc2 chips are required. Figure 5 is the wiring diagram of configuring ep20k200eqi chip with two epc2 chips. Multiple chips can be cascaded conveniently through the ncasc pin of epc2 chip. After the system is powered on, when ep20k200eqi chip detects the jump of nconfig pin level from low to high, start the configuration process. Firstly, the ep20k200eqi chip drives the conf done pin to low, pulls down the NCS pin of the first epc2 and gates the chip. After a time delay300J tester
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